The present invention relates to a semiconductor memory device, and in particular to a full CMOS static RAM device.
The static RAM devices (hereinafter abbreviated as SRAM) using MOS transistors are classified into (1) full CMOS SRAM devices having both memory cells and peripheral circuits constituted by n-MOS transistors and p-MOS transistors; and (2) SRAM devices having memory cells constituted by n-MOS transistors and high resistive loads, and peripheral circuits constituted by CMOS transistors.
FIG. 1 is an equivalent circuit diagram of a memory cell in a full CMOS SRAM and FIG. 2 is an equivalent circuit diagram of a memory cell in a SRAM having its cells constituted by n-MOS transistors.
In FIG. 1, a cell of the full CMOS SRAM comprises a first inverter including a load MOS transistor (p-MOS) Q5 and a driver MOS transistor (n-MOS) Q3; a second inverter including a load MOS transistor (p-MOS) Q6 and a driver MOS transistor (n-MOS) Q4; and transfer MOS transistors (n-MOS's) Q1 and Q2, as is well known.
Reference numerals used in FIG. 1 correspond to those in FIG. 3. The structure (geometrical layout) of the SRAM shown in FIG. 1 will be described with reference to FIGS. 1 and 3.
As shown in FIG. 2, a cell of the SRAM having its cells constituted by n-MOS transistors is different from that of the full CMOS SRAM in that the load MOS transistors Q5 and Q6 of the latter CMOS SRAM are replaced with high value resistors Rl and R2, respectively.
SRAM's having a structure shown in FIG. 2 have heretofore been predominantly used since it is possible to provide a device having a small cell area and a high integration degree.
Recently, industry has been increasingly interested in memory cells in the full CMOS SRAM in a deep submicron age due to the fact that the reliability of the full CMOS SRAM is high, that a current consumed at standby time is low, that the operable range of temperatures is wide and that the device can work even at a low voltage of a power supply.
Various structures of the full CMOS SRAM have been proposed. A full CMOS SRAM having a layout shown in FIG. 3 is proposed in, for example, 1986 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 204-205.
In FIG. 3, the transfer MOS transistor (hereinafter abbreviated as TR-MOS) comprises source/drain regions 71 and 72 and a gate electrode 84 constituting a word line 83 depicted with thick solid lines. The TR-MOS Q2 comprises source/drain regions 75 and 76 and a gate electrode 85 constituting a word line 83.
The driver MOS transistor (hereinafter abbreviated as DV-MOS) Q3 comprises source/drain regions 73 and 74 and a gate electrode 87 constituting an interconnecting conductor 86 (depicted with thick solid lines). The DV-MOS Q4 comprises source/drain regions 76 and 77 and a gate electrode 89 constituting an interconnecting conductor 88 (depicted with thick solid lines).
The load MOS transistor (hereinafter abbreviated as FK-MOS) Q5 comprises source/drain regions 79 and 80 and a gate electrode 89 constituting an interconnecting conductor 86. The FK-MOS Q6 comprises source/drain regions 81 and 82 and a gate electrode 90 constituting an interconnecting conductor 88.
The source/drain region 72 (74) of the TR-MOS Q1 (DV-MOS Q3) is connected with the source/drain region 80 of the FK-MOS Q5 via an interconnecting conductor 68. The source/drain region 72 (74) and 80 are connected with the interconnecting conductor 68 via contact holes 92 and 97, respectively.
Similarly, the source/drain region 76 (78) of the TR-MOS Q2 (DV-MOS Q4) is connected with the source/drain region 81 of the FK-MOS Q6 via an interconnecting conductor 67. The source/drain regions 76 (78) and 81 are connected with the interconnecting conductor 67 via contact holes 94 and 98, respectively.
The source/drain regions 79 and 82 are connected with a power supply line 66 via contact holes 95 and 96.
The source/drain region 73 of the DV-MOS Q3 is connected with a ground line 70 via a contact hole 91. The source/drain region 77 of the DV-MOS Q4 is connected with a ground line 69 via a contact hole 93.
The source/drain region 71 of the TR-MOS Q1 is connected with a data line 62 (FIG. 1) via a contact hole 65. The source/drain region 75 is connected with a data line 63 via a contact hole 64.
In the thus formed six MOS cell as is well known, a parasitic capacity of the source/drain region 72 of the DV-MOS Q3 and a parasitic capacity on the interconnecting conductor 68 connected with the source/drain region 72 and gate electrodes, etc. function as one storing node while a parasitic capacity of the source/drain region 76 of the DV-MOS Q4 and a capacity on the interconnecting conductor 67 connected with the source/drain region 76 and the gate electrodes, etc. function as the other storing node.